We’ve successfully taped out BeamCIM, a cutting-edge mixed-signal Compute-In-Memory (CIM) accelerator optimized for beamforming applications. BeamCIM leverages Linear Embedding (LE) techniques to efficiently transform high-dimensional input data into compact, lower-dimensional features, enabling fast and power-efficient beamforming performance. Designed for next-generation signal processing tasks, BeamCIM pushes the boundaries of speed, scalability, and system integration.

• ADC reduction without beam squinting errors
• MAC and ADC co-design improves power and area efficiency
• Simplified multi-phase clock-generation for scalability
• Fabricated in 28-nm CMOS, 8-element, 2-beam receiver with 7.8 mW and 0.02 mm2 / beam

We developed the first structured-sparse Walsh-Hadamard NN processor with on-chip MRAM, enabling compact, energy-efficient radar inference. Demonstrated on a Cognisense radar workload, the chip integrates a specialized architecture and memory system optimized for sparse-orthogonal computations.

To address MRAM’s leakage and read energy, we use layer-wise power gating and a multi-clocked weight cache, achieving 9.51 TOPS/W at 33% weight density. When applied to a ChirpNet-style radar model, our transform layer delivers 2.4× better performance and 2.1× energy efficiency over recent CNN baselines—with no accuracy loss.