Publications

Book Chapter:

  • A. I. Khan, “Energy-efficient computing with negative capacitance,” in Advanced Nanoelectronics: Post-Silicon Materials and Devices, Muhammad Mustafa Hussain, Ed., Wiley-VCH (2018).
  • A. I. Khan, and S. Salahuddin, “Extending CMOS with negative capacitance,” in CMOS and Beyond: Logic Switches for Terascale Integrated Circuits, T.-J. K. Liu and K. Kuhn, Eds., Cambridge University Press (2015).

Invited talks and tutorials:

  1. The 64th International Electron Devices Meeting (IEDM), San Francisco, 12/03/2018.  “On the microscopic origin of negative capacitance in ferroelectric materials: A toy model” (paper 9.3).
  2. The 234th Electrochemical Society Meeting (AiMES 2018), Cancun, Mexico, 10/01/2018.  “Ferroelectric oxides and negative capacitance for ultra-low power computing”.
  3. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong SAR, China, 7/11/2018.  “Ferroelectric Transistors for Neuromorphic Computing” (online presentation).
  4. Materials Research Society (MRS) Spring Meeting 2018, Phoenix, AZ, 4/2/2018.  “Negative Capacitance FETs: Physics, Materials and Devices”  (Tutorial).
  5. SEMICON Korea, Seoul, Korea, 1/31/2018.  “Negative Capacitance Transistors: Physics, Materials and the State-of-Art.”
  6. Samsung, Seoul, Korea,1/30/2018. “Negative Capacitance Transistors for Ultra-low Power Computing.”
  7. Taiwan Semiconductor Manufacturing Company, Teleseminar, 1/24/2018. “Negative Capacitance Transistors: The next steps.”
  8. imec, Leuven, Belgium. 9/14/2017. “Negative capacitance for ultra-low power computing.”
  9. European Solid State Device Research Conference (ESSDERC), 9/11/2017. “Negative capacitance FETs: Physics, materials and devices” (tutorial).
  10. The Institute of Electronics and Nanotechnology Seminar, Georgia Tech, 8/21/2017. “Negative capacitance technology for ultra-low power computing.”
  11. Micro/Nano- Electronics for Global Challenges Conference with James D. Meindl Distinguished Lecture Series & Monie Ferst Award Symposium, Georgia Tech, Atlanta. 5/23/2017 “Ultra-low Power Computing with New Materials: The Case for Ferroelectric Based Logic and Memory.”
  12. Joint IEEE International Symposium on Applications of Ferroelectrics (ISAF), International Workshop on Acoustic Transduction Materials and Devices (IWATMD), and Piezoresponse Force Microscopy Workshop (PFM), Georgia Tech, Atlanta, 5/11/2017. “Ferroelectrics and  negative Capacitance: What do we know and what do we need to know?”
  13. Material Research Society (MRS) Spring Meeting 2017, 4/19/2017. “Recent advances in negative capacitance for ultra-low power computing.”
  14. International Symposium on Quality Electronic Design (ISQED), 3/15/2016. “Negative capacitance for low power computing.”
  15. IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 10/8/2015. “Negative capacitance in ferroelectric materials and implications for steep transistors.”
  16. Solid State Technology and Devices Seminar, Berkeley. 12/5/2014. “Negative capacitance for ultra-low power beyond-CMOS devices.”
  17. The 32nd International Conference on Physics of Semiconductors (ICPS), 8/13/2014 “Negative capacitance: Exploiting stored energy in ferroelectric materials to break fundamental barriers of energy efficiency in electronic devices.”

Peer Reviewed Publications (Google scholar):

  1. P Wang, AI Khan, S Yu, “Cryogenic behavior of NbO2 based threshold switching devices as oscillation neurons,” Applied Physics Letters (2020)
  2. P Wang, W Shim, Z Wang, J Hur, S Datta, AI Khan, S Yu, “Drain-Erase Scheme in Ferroelectric Field Effect Transistor—Part II: 3-D-NAND Architecture for In-Memory Computing,” IEEE Transactions on Electron Devices (2020)
  3. P Wang, Z Wang, W Shim, J Hur, S Datta, AI Khan, S Yu, “Drain-Erase Scheme in Ferroelectric Field-Effect Transistor–Part I: Device Characterization,” IEEE Transactions on Electron Devices (2020)
  4. Z Wang, H Ying, W Chern, S Yu, M Mourigal, JD Cressler, AI Khan, “Cryogenic characterization of a ferroelectric field-effect-transistor,” Applied Physics Letters (2020)
  5. S. Pentapati, R. Perumal, S. Khandelwal, A. I. Khan and S. K. Lim, “Optimal Ferroelectric Parameters for Negative Capacitance Field-Effect Transistors Based on Full-Chip Implementations—Part II: Scaling of the Supply Voltage,” IEEE Transactions on Electron Devices (2020)
  6. S Pentapati, R Perumal, S Khandelwal, AI Khan, SK Lim, “Cross-domain optimization of ferroelectric parameters for negative capacitance transistors—Part I: Constant supply voltage,” IEEE Transactions on Electron Devices (2019)
  7. Z Wang, AI Khan, “Ferroelectric Relaxation Oscillators and Spiking Neurons,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (2019)
  8. Y. Long, D. Kim, E. Lee, P. Saha, B. A. Mudassar, X. She, A. I. Khan, S. Mukhopadhyay, “A Ferroelectric FET based Processing-in-Memory Architecture for DNN Acceleration,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (2019) (link)
  9. Y. Fang, J. Gomez, Z. Wang, S. Datta, A. I. Khan, A. Raychowdhury. “Neuro-mimetic Dynamics of a Ferroelectric FET Based Spiking Neuron,” IEEE Electron Device Letters (2019) (link)
  10. A. K. Yadav, K. X. Nguyen, Z. Hong, P. García-Fernández, P. Aguado-Puente, C. T. Nelson, S. Das, B. Prasad, D. Kwon, S. Cheema, A. I. Khan, J. Iniguez, J. Junquera, L.-Q. Chen, D. A. Muller, R. Ramesh, S. Salahuddin, “Spatially resolved steady-state negative capacitance,” Nature (2019) (link)
  11. Y. Liu, Z. Wang, T. Orvis, D. Sarkar, R. Kapadia, A. I. Khan, J. Ravichandran, “Epitaxial growth and Dielectric Characterization of Atomically Smooth 0.5Ba(Zr0.2Ti0.8)O3-0.5(Ba0.7Ca0.3)TiO3 thin films,” J. Vac. Sci. Tech. A. 37, 011502 (2019).
  12. Z. Wang, B. Crafton, J. Gomez, R. Xu, A. Luo, Z. Krivokapic, L. Martin, S. Datta, A. Raychowdhury, A. I. Khan, “Experimental Demonstration of Ferroelectric Spiking Neurons for Unsupervised Clustering,” The 64th International Electron Devices Meeting (IEDM 2018), 2018 (paper 13.3, research highlight in Nature Electronics link, pdf ).
  13. A. I. Khan, “On the microscopic origin of negative napacitance in ferroelectric materials: A toy model,” The 64th International Electron Devices Meeting (IEDM 2018), 2018 (invited, paper 9.3).
  14. Y. Long, T. Na, P. Rastogi, K. Rao, A. I. Khan, S Yalamanchili and S. Mukhopadhyay, “A ferroelectric FET based power-efficient architecture for data-intensive computing,” Proc. International Conference on Computer Aided Design (ICCAD), 2018.
  15. N. Tasneem, A. I. Khan, “On the possibility of dynamically tuning and collapsing the ferroelectric hysteresis/memory window in an asymmetric double gate MOS device: A path to a reconfigurable logic-memory device,” Proc. 76th Device Research Conference (DRC), 2018.
  16. Z. Wang*, A. A. Gaskell*, M. Dopita, D. Kriegner, N. Tasneem, J. Mack, N. Mukherjee, Z. Karim, A. I. Khan, “Antiferroelectricity in lanthanum doped zirconia without metallic capping layers and post-deposition/-metallization anneals,” Appl. Phys. Lett. 112, 222902 (2018). (*Equal contribution, Editor’s pick)
  17. M. Hoffmann, A. I. Khan, C. Serrao, Z. Lu, S. Salahuddin, M. Pešić, S. Slesazeck, U. Schroeder, T. Mikolajick. “Ferroelectric negative capacitance domain dynamics,” J. Appl. Phys. 123, 184101 (2018).
  18. Z. Lu, C. Serrao, A. I. Khan, J. D. Clarkson, J .C. Wong, R. Ramesh & S. Salahuddin. “Electrically induced, non-volatile, metal-insulator transition in a ferroelectric-controlled MoS2 transistor,”Appl. Phys. Lett.  112(4), 043107 (2018).
  19. A. I. Khan*, M. Hoffmann*, K. Chatterjee, Z. Lu, R. Xu, C. Serrao, S. Smith, L. W. Martin, C. Hu, R. Ramesh & S.Salahuddin, “Differential voltage amplification from ferroelectric negative capacitance,” Appl. Phys. Lett. 111, 253501 (2017). (Cover article, editor’s pick. *Equal contribution)
  20. Z. Wang, S. Khandelwal & A. I. Khan, “Ferroelectric oscillators and their coupled networks,” IEEE Electron Dev. Lett. 38, 1614 (2017).
  21. K. Chatterjee, S. Kim, G. Karbasian, A. J. Tan, A. K. Yadav, A. I. Khan, C. Hu & S. Salahuddin, “Self-aligned, gate last, FDSOI, ferroelectric gate memory device with 5.5 nm Hf0.8Zr0.2O2, high endurance and breakdown recovery.” IEEE Electron Dev. Lett. 38, 1379 (2017).
  22. X. Li, J. Sampson, A. I. Khan, K. Ma, S. George, A. Aziz, S. K. Gupta, S. Salahuddin, M.-F. Chang, S. Datta & V. Narayanan, “Enabling energy-efficient nonvolatile compu- ting with negative capacitance FET.” IEEE Trans. Electron Dev. 64, 3452 (2017).
  23. A. I. Khan, U. Radhakrishna, S. Salahuddin & D. A. Antoniadis, “Work function engineering for performance improvement in leaky negative capacitance FETs.” IEEE Trans. Electron Dev. 38, 1335 (2017).
  24. S. K Samal, S. Khandelwal, A. I. Khan, S. Salahuddin, C. Hu & S, K. Lim, “Full chip power benefits with negative capacitance FETs.” Proc. 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).
  25. Z. Lu, C. Serrao, A. I. Khan, L. You, J. C. Wong, Y. Ye, H. Zhu, X. Zhang & S. Salahuddin, “Non-volatile MoS2 field effect transistors directly gated by single crystalline epitaxial ferroelectric.” Appl. Phys. Lett. 111, 023104 (2017).
  26. G. Karbasian, A, Tan, A. Yadav, E. M. H. Sorensen, C. R. Serrao, A. I. Khan, K. Chatterjee, S, Kim, C. Hu & S. Salahuddin, “Ferroelectricity in HfO_2 thin films as a function of Zr doping.” Proc. 2017 Int’l Symp. VLSI Technology, Systems and Application (VLSI-TSA).
  27. S. Khandelwal, J. P. Duarte, A. I. Khan, S. Salahuddin & C. Hu, “Impact of parasitic capacitance and ferroelectric parameters on negative capacitance FinFET characteristics.” IEEE Electron Dev. Lett. 38 (1), 142-144.
  28. J. P. Duarte, S. Khandelwal, A. I. Khan, A. Sachid, Y. K. Lin, H. L. Chang, S. Salahuddin & C. Hu, “Compact models of negative-capacitance FinFETs: Lumped and distributed charge models.” Proc. 2016 IEEE International Electron Devices Meeting (IEDM), 30.5.1-30.5.4.
  29. A. I. Khan, U. Radhakrishna, S. Salahuddin & D. Antoniadis. `Negative Capacitance Behavior in a Leaky Ferroelectric,” IEEE Trans. Electron Devices, 66, 4416 (2016).
  30. M. Hoffmann, M Pesic, K. Chatterjee, A. I. Khan, S. Salahuddin, S. Slesazeck, U. Schroeder & T. Mikolajick, “Direct observation of negative capacitance in polycrystalline ferroelectric HfO2.” Adv. Func. Mater. 26, 8643 (2016).
  31. S. George, K. Ma, A. Aziz, X. Li, J. Sampson, A. I. Khan, S. Salahuddin, S. Datta, S. Gupta, and V. Narayanan, “Nonvolatile memory design based on ferroelectric FETs,” Design Automation Conference 2016.
  32. S. Khandelwal, A. I. Khan, J. P. Duarte, A. Sachid, S. Salahuddin, & C. Hu. “Circuit Performance Analysis of Negative Capacitance FinFETs.” Proc. 2016 Symposia on VLSI Technology.-.1in
  33. S. Bakaul, C. Serrao, M. Lee, C. W. Yeung, A. Sarker, S.-L. Hsu, A. Yadav, L. Dedon, L. You, A. I. Khan, J. Clarkson, C. Hu, R. Ramesh, S. Salahuddin, “Single crystal ferroelectric oxide devices on silicon,” Nature Comm. 7, 10547 (2016).
  34. C.-I. Lin, A. I. Khan, S. Salahuddin and C. Hu, “Design of ferroelectric negative capacitance FETs and sensitivity to material variations,” IEEE Trans. Electron Dev. 63, 2197 (2016).-.1in
  35. A. I. Khan, K. Chatterjee, J. P. Duarte, Z. Lu, A. Sachid, S. Khandelwal, R. Ramesh, C. Hu & S. Salahuddin.“ Negative capacitance in short channel FinFETs externally connected to an epitaxial ferroelectric capacitor,” IEEE Electron Dev. Lett. 37, 111 (2016).
  36. A. I. Khan & S. Salahuddin, “Negative capacitance in ferroelectric materials and implications for steep transistors.” Proc. 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
  37. A. I. Khan, K. Chatterjee, R. Ramesh & S. Salahuddin, “Understanding negative capacitance dynamics in ferroelectric capacitors.” Proc. 2015 Fourth Berkeley Symposium on Energy Efficient Electronic Systems (E3S).
  38. C. Hu, S. Salahuddin, C.-I. Lin and A. I. Khan, “0.2V adiabatic negative capacitance FinFET with 0.6 mA/um ION and 0.1 nA/um IOFF,” Proc. 73rd Annual Device Research Conference (DRC), pp. 39 (2015).
  39. A. I. Khan, X. Marti, C. Serrao, R. Ramesh & S. Salahuddin, “ Voltage controlled ferroelastic switching in Pb(Zr0.2Ti0.8)O3 thin films,” Nano Lett. 15, 2229 (2015).
  40. A. I. Khan, K. Chatterjee, B. Wang, S. Drapcho, L. You, C. Serrao, S. R Bakaul, R. Ramesh, & S. Salahuddin.“Negative capacitance in a ferroelectric capacitor,” Nature Materials 14, 182 (2015). (Nature Materials News and Views, Press coverage at the National Science Foundation, CITRIS-UC, Phys.org, etc.)
  41. W. Gao, A. I. Khan, X. Marti, C. Nelson, C. Serrao, J. Ravichandran, R. Ramesh, & S. Salahuddin.“Room-temperature negative capacitance in a ferroelectric-dielectric superlattice heterostructure,” Nano Lett. 14, 5814 (2014).
  42. A. I. Khan, P. Yu, M. Trassin, M. J. Lee, L. You, & S. Salahuddin.“The effects of strain relaxation on the dielectric properties of epitaxial ferroelectric Pb(Zr0.2Ti0.8)TiO3 thin films,” Appl. Phys. Lett. 105, 022903 (2014).
  43. A. I. Khan, D. E. Nikonov, S. Manipatruni, T. Ghani, & I. A. Young.“ Voltage induced magnetostrictive switching of nanomagnets: Strain assisted spin transfer torque random access memory,” Appl. Phys. Lett. 104, 262407 (2014).
  44. C. Yeung, A. I. Khan, J.-Y. Cheng, S. Salahuddin & C. Hu, “Low power negative capacitance FETs for future quantum-well body technology,” Proc. Intl. Conf. VLSI Technology, Systems, and Applications (VLSI-TSA), pp. 1 (2013). (Best paper award.)
  45. K. Liu, D. Fu, J. Cao, J. Suh, K. X. Wang, C. Cheng, D. F. Ogletree, H. Guo, S. Sengupta, A. I. Khan, C. W. Yeung, S. Salahuddin, M. M. Deshmukh, & J. Wu, “Dense electron system from gate-controlled surface metal-insulator transition,” Nano Lett., 12, 6272 (2012).
  46. C. Yeung, A. I. Khan, J.-Y. Cheng, S. Salahuddin & C. Hu, “ Non-hysteretic negative capacitance FET with sub-30mV/dec swing over 106 times current range and I_ON of 0.3 mA/mum without strain enhancement at 0.3 V VDD,” Proc. Intl. Conf. Simulation of Semiconductor Processes and Devices (SISPAD), pp. 257 (2012).
  47. A. I. Khan, C. W. Yeung, C. Hu, & S. Salahuddin. “Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation,” Proc. Intl. Electron Devices Meeting (IEDM), pp. 11-3 (2011).
  48. A. I. Khan, D. Bhowmik, Pu Yu, S. J. Kim, X. Pan, R. Ramesh, & S. Salahuddin. “Experimental evidence of ferroelectric negative capacitance in nanoscale hetero- structures,” Appl. Phys. Lett. 99, 113501 (2011). (Cover article, Most notable 50 APL papers in 2009-11, Press coverage at UCBerkeley NewsCenter, CNET.com, Phys.org etc.)
  49. S. C. Kehr, Pu Yu, Y.M. Liu, M. Parzefall, A. I. Khan, R. Jacob, M.T. Wenzel, H.-G. Ribbeck, M. Helm, X. Zhang, L.M. Eng, & R. Ramesh. “Microspectroscopy on perovskite-based superlenses,” Opt. Mat. Express 1, 1051 (2011).
  50. A. K. Biswas, S. Chowdhury, M. M. M. Khan, M. Hasan & A. I. Khan. “Some basic ternary operations using Toffoli gates along with the cost of implementation,” Proc. IEEE Intl. Symp. Multiple-Valued Logic (ISMVL), pp. 142 (2011).
  51. M. M. M. Khan, A. K. Biswas, S. Chowdhury, M. Hasan & A. I. Khan. “Synthesis of GF (3) based reversible/quantum logic circuits without garbage output,” Proc. IEEE Intl. Symp. Multiple-Valued Logic (ISMVL), pp. 98 (2009).
  52. M. K. Ashraf, A. I. Khan, & A. Haque, “Wave function penetration effects on ballistic drain current in double gate MOSFETs fabricated on (100) and (110) silicon surfaces,” Solid. State Electron. 53, 271 (2009).
  53. A. I. Khan, M. K. Ashraf, & A. Haque, “Wave function penetration effects in double gate metal-oxide-semiconductor field-effect-transistors: impact on ballistic drain current with device scaling,” J. Appl. Phys. 105, 064505 (2009).
  54. A. I. Khan, N. Nusrat, S. M. Khan, M. Hasan, & M. H. A. Khan. “Quantum realization of some ternary circuits using Muthukrishnan-Stroud gates,” Proc. IEEE Intl. Symp. Multiple-Valued Logic (ISMVL), pp. 20 (2007).
  55. C. Yeung, A. I. Khan, J.-Y. Cheng, S. Salahuddin & C. Hu, “Low power negative capacitance FETs for future quantum-well body technology,” Proc. Intl. Conf. VLSI Technology, Systems, and Applications (VLSI-TSA), pp. 1 (2013). (Best paper award.)
  56. K. Liu, D. Fu, J. Cao, J. Suh, K. X. Wang, C. Cheng, D. F. Ogletree, H. Guo, S. Sengupta, A. I. Khan, C. W. Yeung, S. Salahuddin, M. M. Deshmukh, & J. Wu, “Dense electron system from gate-controlled surface metal-insulator transition,” Nano Lett., 12, 6272 (2012).
  57. C. Yeung, A. I. Khan, J.-Y. Cheng, S. Salahuddin & C. Hu, “ Non-hysteretic negative capacitance FET with sub-30mV/dec swing over 106 times current range and I_ON of 0.3 mA/mum without strain enhancement at 0.3 V VDD,” Proc. Intl. Conf. Simulation of Semiconductor Processes and Devices (SISPAD), pp. 257 (2012).
  58. A. I. Khan, C. W. Yeung, C. Hu, & S. Salahuddin. “Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation,” Proc. Intl. Electron Devices Meeting (IEDM), pp. 11-3 (2011).
  59. A. I. Khan, D. Bhowmik, Pu Yu, S. J. Kim, X. Pan, R. Ramesh, & S. Salahuddin. “Experimental evidence of ferroelectric negative capacitance in nanoscale hetero- structures,” Appl. Phys. Lett. 99, 113501 (2011). (Cover article, Most notable 50 APL papers in 2009-11, Press coverage at UCBerkeley NewsCenter, CNET.com, Phys.org etc.)
  60. S. C. Kehr, Pu Yu, Y.M. Liu, M. Parzefall, A. I. Khan, R. Jacob, M.T. Wenzel, H.-G. Ribbeck, M. Helm, X. Zhang, L.M. Eng, & R. Ramesh. “Microspectroscopy on perovskite-based superlenses,” Opt. Mat. Express 1, 1051 (2011).
  61. A. K. Biswas, S. Chowdhury, M. M. M. Khan, M. Hasan & A. I. Khan. “Some basic ternary operations using Toffoli gates along with the cost of implementation,” Proc. IEEE Intl. Symp. Multiple-Valued Logic (ISMVL), pp. 142 (2011).
  62. M. M. M. Khan, A. K. Biswas, S. Chowdhury, M. Hasan & A. I. Khan. “Synthesis of GF (3) based reversible/quantum logic circuits without garbage output,” Proc. IEEE Intl. Symp. Multiple-Valued Logic (ISMVL), pp. 98 (2009).
  63. M. K. Ashraf, A. I. Khan, & A. Haque, “Wave function penetration effects on ballistic drain current in double gate MOSFETs fabricated on (100) and (110) silicon surfaces,” Solid. State Electron. 53, 271 (2009).
  64. A. I. Khan, M. K. Ashraf, & A. Haque, “Wave function penetration effects in double gate metal-oxide-semiconductor field-effect-transistors: impact on ballistic drain current with device scaling,” J. Appl. Phys. 105, 064505 (2009).
  65. A. I. Khan, N. Nusrat, S. M. Khan, M. Hasan, & M. H. A. Khan. “Quantum realization of some ternary circuits using Muthukrishnan-Stroud gates,” Proc. IEEE Intl. Symp. Multiple-Valued Logic (ISMVL), pp. 20 (2007).