Welcome to the Georgia Tech 3D Systems Packaging Research Center!
Since the invention of the integrated circuit (IC) in 1958, there has never been a more exciting time for the field of ‘electronic packaging’ than today. Our field is going through a Renaissance period of innovation and advancement – and it is happening at a remarkable pace. This innovation is driven by new and radical shifts in the semiconductor industry which include 1) conventional packaging architectures have become a principal limiter to system performance, energy efficiency, formfactor, and cost as we continue to scale; and 2) Moore’s Law scaling is slowing due to physical, technological, and economical challenges. Device-circuit-system co-design has never been so critical in offering the optimal cost/performance/power dissipation and thus, improvements in the IC alone without disruptive paradigms in packaging will yield electronic systems that fail by progressively greater margins to reach ‘intrinsic limits’ of each technology node . As a result, the field of packaging has taken center stage today; there is little doubt that packaging in the new era of Moore’s Law will offer extreme levels of die integration/bonding and begin to blur the boundary between on- and off-chip connectivity (especially in 3D architectures) due to ever denser physical I/O interfaces/bonds. This new form of ‘packaging’ is often referred to as ‘Heterogeneous Integration’ or HI today; at Georgia Tech, we have often called this polylithic integration . It is interesting to note that the critical need for such co-design and ‘optimal partitioning’ of circuits and advanced packaging was projected, in-part, by Gordon Moore in his famous paper, “Cramming More Components onto Integrated Circuits” , which forms the basis of Moore’s Law. He states that “The total cost of making a particular system function must be minimized … [at some point] It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected. The availability of large functions, combined with functional design and construction, should allow the manufacturer of large systems to design and construct a considerable variety of equipment both rapidly and economically.” Where monolithic integration forms all circuit functions on a single common semiconductor (at the wafer scale), heterogenous integration enables the concatenation of ‘chiplets’ of various functionalities (logic, I/O, memory, power conversion, passives, photonics, mm-wave, etc.) and materials in a manner that mimics/exceeds monolithic-like performance and utilizing advanced off-chip ‘2.5D’ and ‘3D’ interconnects and packaging to provide ﬂexibility in fabrication and design, improved scalability, reduced development time, and reduced cost. This approach is becoming widely accepted commercially. In fact, a cost-benefit analysis of monolithic die disaggregation was recently performed at the 3 nm node and showed that chiplets become cost competitive when monolithic die size exceeds 150 mm2 due to yield considerations of larger monolithic die .
As a result, heterogeneous integration offers ‘fertile grounds’ for radical new thinking in system integration and microarchitectures that will drive cost, functionality, energy and performance gains for the next era of Moore’s Law in applications that include artificial intelligence, 5G/6G, internet-of-things, healthcare, and sensor systems. The mission of the Georgia Tech 3D Systems Packaging Research Center is to help shape and define the technological landscape of future heterogeneously integrated electronic systems for these applications.
The center’s core technological expertise resolves around 2.5D and 3D HI systems enabled by glass-panel based, silicon based, and organic-based technologies. Our glass-panel based substrate technologies offer several benefits that include large-scale substrates beyond reticle-size limits, die-embedding within the glass-core, embedded cooling, ultra-low loss and dense interconnects, and low-cost panel scale processing. We have demonstrated our glass-core substrate technologies for digital and mm-wave applications. We take great pride in working with our industry partners not only on exciting research applications enabled by glass-core substrates, but also in transition some of the key glass-core substrate technologies. We also offer significant expertise in silicon-based HI, including silicon interposers, wafer-scale reconstituted chiplet tiers, chiplet-to-wafer bonding, etc. Further, GT has unique technologies and processes for bridge-chip based interconnection architectures for digital, mm-wave, and photonic chiplets. Lastly, the center offers core expertise in circuit-system co-design and optimal partitioning of monolithic vs. polylithic HI systems, accounting power, performance, and cost metrics that have been used for glass-based and silicon-based 2.5D/3D architectures.
Our center thrives on interdisciplinary research supported by academic faculty, research faculty, and students from multiple schools across campus, including Georgia Tech Research Institute (GTRI). This is necessary due to the electrical, mechanical, thermal, and material science complexities that are intrinsic to our field, especially as we transition to even denser, higher power, and higher performance electronic systems. Partnership with industry and translational research are key for our center mission.
Workforce development is paramount to our mission. Our center supports the research and education of PhD, MS, and undergraduate level students from many academic units across campus. Further, in partnership with several academic units across campus, including electrical and computer engineering, mechanical engineering, and materials science and engineering, PRC faculty teach many graduate and undergraduate level courses that span fundamentals, design, technologies, and applications all related to HI (2.5D and 3D) and advanced packaging. Some of these courses also offer labs sections to our students so they gain hands-on training experience in the processes, technologies, and tools/equipment that are intrinsic to the field of HI and advanced packaging (flip-chip bonders, wire-bonders, underfill dispense, wafer-bonders, microfabrication processes, etc.). These courses, combined with more traditional electrical engineering course, help students understand the semiconductor manufacturing and design process from devices, interconnects, circuits, HI/packaging, and system integration.
Thank you for visiting the Georgia Tech 3D Systems Packaging Research Center. We look forward to hearing from you!
 M. Bakir, B. Dang and J. D. Meindl, “Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems,” 2007 IEEE Custom Integrated Circuits Conference, 2007, pp. 421-428.
 M. Bakir, “Bridge-chip interconnect technologies,” Online IEEE EPS Article, 2021: Bridge-chip Interconnect Technologies – IEEE Electronics Packaging Society
 Gordon E. Moore, “Cramming More Components onto Integrated Circuits,” Electronics, pp. 114–117, April 19, 1965.
 K. Kim, “The smallest engine transforming humanity: the past, present, and future,” in Proc. IEEE International Electron Devices Meeting (IEDM), 2021.