Profile

Hey! I am a 3rd year Ph.D student advised by Prof. Azad Naeemi.

My research focuses on PDK design, mixed signal IC design, and EDA algorithms for 2D and 3D IC at advanced tech nodes (VLSI). I am very grateful to have collaborated with Samsung (2020 – 2024), SK Hynix (2019 – 2021), and others to conduct research in advanced nanoscale devices and in EDA.

Publications

• Device Design Guidelines of 3-nm Node Complementary FET (CFET) in Perspective of Electrothermal Characteristics
  Seung-Geun Jung, Dongwon Jang, Seong-Ji Min, Euyjin Park, Hyun-Yong Yu
  IEEE Access, 2022.

• Methods and systems for predicting the impact of traps on semiconductor devices
  Hyun-Yong Yu, Seung-Geun Jung, Muyeong Son, Dongwon Jang
  Korea Patent, 10-2370795, 2022.

• Performance Analysis on Complementary FET (CFET) Relative to Standard CMOS With Nanosheet FET
  Seung-Geun Jung, Dongwon Jang, Seong-Ji Min, Euyjin Park, Hyun-Yong Yu
  IEEE Journal of the Electron Devices Society, 2021.

• Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)
  Dongwon Jang, Seung-Geun Jung, Seong-Ji Min, Hyun-Yong Yu
  IEEE Access, 2021.

• Analysis of Self-Heating Effects in Monolithic Complementary FET (CFET)
  Dongwon Jang, Seung-Geun Jung, Hyun-Yong Yu
  The 28th Korean Conference on Semiconductors (KCS), 2021.

Research Experience

• Graduate Research Assistant, ECE, Georgia Institute of Technology, 2022 – Present
  • GT3 – Open Source Process-Aware PDK Design for 3nm Tech Node (CoCoSys, 2024 – Present)
  • Heterogeneous 3D Monolithic Processor-In-Memory Design Utilizing Thin-Layer Transfer (Samsung SAIT, Suwon, Korea, 2023 – 2024)
  • Investigating Potential Performance Benefits and Design Feasibility of 3D IC at 3nm Tech (Samsung Semiconductor Inc., San Jose, CA, 2022 – 2024)

• Full-Time Researcher, Institute of Advanced Materials, Inha University, 2021 – 2022
  • PDK Generation and IC Physical Design for 3nm Tech (Samsung Semiconductor Inc., San Jose, CA, 2021 – 2022)

• Graduate Research Assistant, EE, Korea University, 2019 – 2021
  • Device-Circuit Level Modeling and Design Optimization of 3D Monolithic CFET Devices (Samsung Electronics, Suwon, Korea, 2020 – 2021)
  • Investigation of Fermi-Level Pinning Effects in Silicide Contacts Using Ab-initio Simulations (SK Hynix, Icheon, Korea, 2019 – 2021)
  • 3nm Transistor Random Variation Modeling and Analysis at the Atomic-Device-Circuit Levels (Korean Ministry of Trade, Industy and Energy, Sejong, Korea, 2019 – 2021)

Education

• Ph.D, Georgia Institute of Technology, Atlanta, GA, United States, Aug. 2022 – Present
  Electrical and Computer Engineering
  Advisor: Dr. Azad Naeemi

• M.S., Korea University, Seoul, Republic of Korea, Sep. 2019 – Aug. 2021
  Electrical Engineering
  Thesis: Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)
  Advisor: Dr. Hyun-Yong Yu

• B.S., Korea University, Seoul, Republic of Korea, Mar. 2013 – Aug. 2019
  Electrical Engineering