I am an Assistant Professor at the Department of Electrical and Computer Engineering (ECE) at the Georgia Institute of Technology (GaTech) since 2021. Before that, I am a postdoctoral researcher in ECE, GaTech, from Sep. 2020 to Aug. 2021, and a postdoctoral researcher in ECE at the University of Illinois at Urbana-Champaign (UIUC), under the supervision of Prof. Deming Chen. I got my Ph.D. in Electrical Engineering from Waseda University in 2017, under the supervision of Prof. Takeshi Yoshimura. I got my MS and BS degrees in Computer Science and Engineering from Shanghai Jiao Tong University.
I am directing the Software/Hardware Co-design lab (Sharc) in the ECE department at Georgia Tech — twice efforts, 20 to 2000 times better!
I am looking for excellent students interested in the joint area of hardware design (FPGA, ASIC, etc.) and machine learning (DNNs, GNNs, etc.). I also have a broad interest in computer architecture, graph computation, and electronic design automation (HLS, etc.).
- Software/hardware co-design: hardware-efficient machine learning algorithms and neural architecture search (NAS), ML/system co-design, on-device AI
- High-performance reconfigurable computing: FPGA, embedded system, IoT, and edge computing
- Graph computing: efficient algorithms and hardware for large-scale graph computation
- Electronic design automation (EDA): high-level synthesis (HLS), domain-specific HLS
The latest news is maintained here…
- [2021. 09] Callie serves on the TPC of DAC’22.
- [2021. 05] Callie serves on the TPC of ICCD’21 and ASAP’21.
- [2021. 04] Callie serves on the TPC of ICCAD’21.
- [2021.03] Our paper “ScaleHLS: Achieving Scalable High-Level Synthesis through MLIR” is accepted by LATTE’21.
- [2021.03] Our survey paper “Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Co-design” is accepted by IEEE Design & Test magazine.
- [2021.02] Our paper “MeLoPPR: Software/Hardware Co-design for Memory-efficient Low-latency Personalized PageRank” is accepted by DAC’21. Many thanks to my collaborators: Dr. Yao Chen and Dr. Pan Li.
- [2020. 10] Callie serves on the TPC of DAC’21.
- [2020. 11] Our paper “Workload-aware approximate computing configuration” is accepted by DATE’21. Congratulations to my collaborators: Dr. Xun Jiao and his team!
- [2020. 10] Callie serves on the TPC of ICCD’20, DATE’21, and SRC@ICCAD’20.
- [2020. 07] Our team iSmart won 3rd place in DAC-SDC’20, a real-time FPGA-based object detection competition. [results]
- [2020. 05] Our paper “VecQ: minimal loss DNN model compression with vectorized weight quantization” is accepted by IEEE Transactions on Computers (TC). [pdf]
- [2020. 02] Our paper “EDD: Efficient Differentiable DNN architecture and implementation co-search for embedded AI solution” is accepted by DAC’20. [pdf] [slides] [presentation]
- [2020. 01] Our paper “SkyNet: a hardware-efficient method for object detection and tracking on embedded systems” is accepted by the 2020 Conference on Machine Learning and Systems (SysML).
- [2019. 06] Our DNN design strategy (bi-directional co-design approach) won the Best Poster Award at ICML’19 Joint Workshop on On-Device Machine Learning & Compact Deep Neural Network Representations (ODML-CDNNR).
- [2019. 06] Our team won a double-championship in DAC-SDC’19! iSmart3 design won 1st place in the FPGA track, and SkyNet design won 1st place in the GPU track. [Github]
- [2019. 02] Our paper “FPGA/DNN co-design: an efficient design methodology for IoT intelligence on the edge” is accepted by DAC’19.
- [2018. 06] Our iSmart2 team won 3rd place in DAC-SDC’18 in the FPGA track!
- [2017. 12] I joined the ECE department at the University of Illinois Urbana-Champaign (UIUC) as a postdoc and started to work with Prof. Deming Chen.
- [2017. 07] I started my position at Waseda University as an invited researcher with Prof. Takeshi Yoshimura.
- [2017. 07] I defended my dissertation and got my Ph.D. from Waseda University, Japan. Many thanks to my supervisor, Prof. Takeshi Yoshimura.