I am currently a PhD student in Electrical and Computer Engineering at Georgia Institute of Technology. My advisor is Dr. Tushar Krishna. I joined Georgia Tech in Fall 2019 after completing Bachelor of Engineering in Electronics and Instrumentation Engineering from Birla Institute of Technology and Science, Pilani.
My research focusses on Domain-Specific Accelerators and Mapping for AI, Graph and HPC Applications. My general research interests include Computer Architecture, Programmable Spatial Accelerators, Domain-Specific Accelerators for AI/HPC and On-chip Networks.
Click here for my CV.
Experience
Research Intern at IBM Research – TJ Watson Center, Yorktown Heights, NY, USA (May 2024 – Aug 2024)
Part-time Student Researcher at Meta Reality Labs; Atlanta, GA, USA (Aug 2022 – Nov 2022)
Research Scientist Intern at Meta Reality Labs; Sunnyvale, CA, USA (May 2022 – Aug 2022)
Education
PhD in Electrical and Computer Engineering at Georgia Institute of Technology
Advisor – Dr. Tushar Krishna.
Duration – 2021 to Present
GPA – 4/4
Master’s in Electrical and Computer Engineering at Georgia Institute of Technology
Advisor – Dr. Tushar Krishna.
Duration – 2019 to 2021
Master’s Thesis – Understanding the Design Space of Dataflows for Graph Neural Network Accelerators
GPA – 4/4
Bachelor’s in Electronics and Instrumentation Engineering at Birla Institute of Technology and Science, Pilani
Duration – 2015 to 2019
GPA – 9.29/10
Selected Publications and Pre-prints
Google Scholar
Francisco Muñoz-Martínez, Raveesh Garg, José L. Abellán, Michael Pellauer, Manuel E. Acacio, and Tushar Krishna. “Flexagon: A Multi-Dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing”, in Proceedings of the 28th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2023). [Published Paper Link][Arxiv Link]
Raveesh Garg, Eric Qin, Francisco Muñoz-Martínez, Robert Guirado, Akshay Jain, Sergi Abadal, José L Abellán, Manuel E Acacio, Eduard Alarcón, Sivasankaran Rajamanickam, and Tushar Krishna. “Understanding the Design-Space of Sparse/Dense Multiphase GNN dataflows on Spatial Accelerators”, 36th IEEE International Parallel & Distributed Processing Symposium (IPDPS 2022). [Published Paper Link] [ArXiv Link]
Best Paper Nominee [Top 5 from 474 submissions]
Raveesh Garg, Michael Pellauer, Sivasankaran Rajamanickam, and Tushar Krishna. “Exploiting Inter-Operation Data Reuse in Scientific Applications using GOGETA”, arXiv preprint arXiv:2303.11499 (2023) [Arxiv Link]
Eric Qin, Raveesh Garg, Abhimanyu Bambhaniya, Michael Pellauer, Angshuman Parashar, Sivasankaran Rajamanickam, Cong Hao, and Tushar Krishna. “Enabling Flexibility for Sparse Tensor Acceleration via Heterogeneity.” arXiv preprint arXiv:2201.08916 (2022). [ArXiv Link]
Artifacts
OMEGA: A simulation Framework for Observing Mapping Efficiency over GNN Accelerators [github]
Workshops and Tutorials
Tutorial (Organizer and Presenter) at ASPLOS 2023: Enabling Detailed Cycle-Level Simulation of AI and HPC Applications with Detailed Memory Hierarchy using STONNE, OMEGA and SST-STONNE [Website]
Tutorial (Organizer and Presenter) at ASPLOS 2022: STONNE+OMEGA: Cycle-level Simulation of Dense/Sparse DNN and GNN Accelerators [Website]
Young Architect Workshop (Author and Presenter) at ASPLOS 2022: A Communication-Centric Dataflow Accelerator for High-Performance Conjugate Gradient. [Lightning talk]
ModSim 2022 (Author and Presenter): SST-STONNE: Enabling cycle-level simulation of flexible spatial accelerators for DNNs and GNNs with a detailed memory hierarchy.
Invited Talks
Minisymposium “Co-Design of Data Flow Accelerators for Scientific Simulations and Machine Learning” at SIAM PP’22. Talk title: Understanding the Design Space of Sparse/Dense Multiphase Dataflows for Mapping Graph Neural Networks on Spatial Accelerators [Abstract].
Awards and Honors
Best Paper Award Nominee at IPDPS 2022 [Top 5 from 474 submissions]
Contact
Email: raveesh <dot> g <at> gatech <dot> edu