The third Young Architect Workshop (YArch ’21, pronounced “why arch”) will provide a forum for junior graduate students studying computer architecture and related fields to present early stage or on-going work and receive constructive feedback from experts in the field as well as from their peers. Students will also receive mentoring opportunities in the form of keynote talks, a panel discussion geared toward grooming young architects, and 1-on-1 meetings with established architects.
Students will receive feedback from experts both about their research topic in general and more specifically, their research directions. Students will also have an opportunity to receive valuable career advice from leaders in the field and to network with their peers and develop long-lasting, community-wide relationships.
YArch is organized in conjunction with the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2021).
YArch’s main event will take place on April 13th. We have also planned a round-table mentoring event for students and senior architects on April 21st. All YArch activities will be held online, using Zoom and GatherTown. Please look for links to these meetings on YArch’s page on Clowdr (the platform hosting the entirety of ASPLOS).
Main event: Tuesday, April 13th (All times in US Eastern)
9:45 – 10:00 | Opening Remarks (on Zoom)
10:00 – 11:00 | Keynote 1 (on Zoom)
Career Choices: A Personal Perspective
Joel Emer (MIT)
11:00 – 12:00 | Poster Session 1 (on GatherTown)
High-Throughput Persistence with Coroutines
Marina Vemmou (Georgia Tech)
Quantum Von Neumann Architectural Modeling for Algorithm Analysis
Alan Robertson (Univ. Sydney)
Efficient Architectural Support for Automated False Sharing Detection and Repair
Vipin Patel (IIT Kanpur)
Architectural Implications of Graph Neural Networks for Recommendation
Samuel Hsia (Harvard)
Run-Time Analytical Modeling-Based Hardware Trojan Detection for Secure Processor
Burin Amornpaisannon (National Univ. Singapore)
12:00 – 12:15 | Break
12:15 – 13:15 | Keynote 2 (on Zoom)
Habits for Happy Success: Reflections from My Anti-Bio
Sarita Adve (Univ. Illinois Urbana-Champaign)
13:15 – 14:15 | Poster Session 2 (on GatherTown)
Efficient Formal Verification of Hardware Memory Consistency
Yao Hsiao (Stanford)
Improving GPU Utilization in ML Workloads Through Finer-Grain Synchronization
Reese Kuper, Suchita Pati (Univ. Wisconsin)
Architectures for Secure High-Performance Computing
Ayaz Akram (UC Davis)
Investigating the Potential for Near Data Processing to Reduce Secure Memory Overheads
Casey Nelson (Brown Univ.)
Prefetch-PathORAM: A Dynamic Superblock Scheme for PathORAM
Yongqin Wang, Rachit Rajat (Univ. Southern California)
14:15 – 14:30 | Break
14:30 – 16:00 | Panel (on Zoom)
Demystifying Grad School
Panelists: Shaizeen Aga (AMD Research), Irina Calciu (VMWare Research), Samira Khan (University of Virginia), Moinuddin Qureshi (Georgia Institute of Technology), Josep Torrellas (Univ. Illinois at Urbana-Champaign)
Moderator: Adrian Sampson (Cornell)
16:00 – 16:10 | Closing Remarks (on Zoom)
Round-Table Mentoring event: Wednesday, April 21st
12:00 – 13:00 (US Eastern) | On GatherTown
Keynote 1 – Career Choices: A Personal Perspective (Recording)
Speaker: Joel Emer (Massachusetts Institute of Technology / Nvidia)
Abstract: A career in computer architecture involves many decisions… should I work in industry or academia (or both)… how do I pick a good research topic… and many others. While the “right” answers to these decisions will vary from person to person, I believe that it is important to try to understand the relevant factors behind each such decision so one can weigh them and come to an answer that is likely to best meet one’s own needs. In this talk, I will try to illustrate my thoughts on some of these factors through the lens of my own career and highlight the factors that I’ve observed and considered over the years.
Bio: For over 40 years, Joel Emer held various research and advanced development positions investigating processor micro-architecture and developing performance modeling and evaluation techniques. He has made architectural contributions to a number of VAX, Alpha and X86 processors and is recognized as one of the developers of the widely employed quantitative approach to processor performance evaluation. More recently, he has been recognized for his contributions in the advancement of deep learning accelerator design, spatial and parallel architectures, processor reliability analysis, cache organization and simultaneous multithreading. Currently he is a professor at the Massachusetts Institute of Technology and spends part time as a Senior Distinguished Research Scientist in Nvidia’s Architecture Research group. Previously, he worked at Intel where he was an Intel Fellow and Director of Microarchitecture Research. Even earlier, he worked at Compaq and Digital Equipment Corporation. He earned a doctorate in electrical engineering from the University of Illinois in 1979. He received a bachelor’s degree with highest honors in electrical engineering in 1974, and his master’s degree in 1975 – both from Purdue University. Among his honors, he is a Fellow of both the ACM and IEEE, and a member of the NAE. In 2009 he was recipient of the Eckert-Mauchly award for lifetime contributions in computer architecture.
Time: Tuesday, April 13th 2021, 10:00-11:00am (US Eastern)
Keynote 2 – Habits for Happy Success: Reflections from My Anti-Bio (Recording)
Speaker: Sarita Adve (Univ. Illinois at Urbana-Champaign)
Abstract: A PhD is not an end in itself. It is often an intense experience that solidifies habits that affect one’s happiness and the shape of one’s success for years to come. The secret to the habits for your happy success is yours alone. I will discuss some habits that have stood by me by reflecting on my anti-bio – the failures that you won’t see in my bio.
Bio: Sarita Adve is the Richard T. Cheng Professor of Computer Science at the University of Illinois at Urbana-Champaign. Her research interests span the system stack, ranging from hardware to applications. Her early work on data-race-free memory consistency models and later work on the memory models for the Java and C++ programming languages form the foundation for memory models used in most hardware and software systems today. She is also known for her work on heterogeneous computing and software-driven approaches for hardware resiliency. Most recently, her group released ILLIXR (Illinois Extended Reality testbed), the first fully open source extended reality (XR) system to democratize XR systems research, development, and benchmarking. She is a member of the American Academy of Arts and Sciences, a fellow of the ACM and IEEE, and a recipient of the ACM/IEEE-CS Ken Kennedy award, the Anita Borg Institute Women of Vision award in innovation, the ACM SIGARCH Maurice Wilkes award, and the University of Illinois campus award for excellence in graduate student mentoring. As ACM SIGARCH chair, she co-founded the CARES movement, winner of the CRA distinguished service award, to address discrimination and harassment in Computer Science research events. She received her PhD from the University of Wisconsin-Madison and her B.Tech. from the Indian Institute of Technology, Bombay.
Time: Tuesday, April 13th 2021, 12:15-1:15pm (US Eastern)
Title: Demystifying Grad School (Recording)
Time: Tuesday, April 13th 2021, 2:30-4:00pm (US Eastern)
Interests: processor architectures, memory subsystems and security with a specific interest in near-memory accelerators
Bio: Shaizeen Aga is a Technical Lead and Member of Technical Staff at AMD Research where she leads a team focused on application-driven design of accelerators and future architectures. She obtained her Masters (2013) and Ph.D. (2017) from the University of Michigan, Ann Arbor. Her research has been published at several top-tier computer architecture venues (ISCA, MICRO, HPCA) and also at high-performance computing venues (SC). Her work has won several awards at and across institutional level and she was an invited participant in Rising Stars in EECS, 2017 workshop. She is also a (co-)inventor on over 15 granted and pending US patents. She is passionate about mentoring and is the co-founder of Young Architect Workshop series which she co-organized at HPCA 2019 and ASPLOS 2020.
Interests: parallel and distributed systems and algorithms, rack-scale systems, multicore synchronization, concurrent data structures, hardware support for rack-scale systems
Bio: Irina Calciu is a senior researcher at VMware Research working on systems and algorithms for rack-scale computing. Irina has co-authored papers at top conferences, obtaining Best Paper awards at ASPLOS and TRANSACT, and was awarded a Kanellakis Fellowship in 2014. Irina completed her PhD at Brown University in 2015, working with Maurice Herlihy and Justin Gottschlich (Intel Labs) on algorithms for non-uniform memory access (NUMA) architectures and hybrid transactional memory. Prior to VMware, she has been a visiting researcher at Intel Labs and a research intern at Microsoft Research.
Panelist: Samira Khan (University of Virginia)
Interests: emerging technologies, memory, accelerators, systems
Bio: Samira Khan is an Assistant Professor at the University of Virginia. Her research group, ShiftLab, is motivated to introduce a paradigm shift in our current computing model. She is an architect at heart and builds software-hardware stacks for emerging technologies. Her group takes pride in producing system artifacts, FPGA prototypes, and new simulators. Currently, she is visiting Google Brain and working with some awesome people at Google with a mission to change the world. She hosts “Happy Hour with Architects“, which is a platform to discuss and debate architecture trends and future directions with prominent people in academia and industry.
Panelist: Moinuddin Qureshi (Georgia Institute of Technology)
Interests: computer architecture, memory systems, hardware security, quantum computing
Bio: Moinuddin Qureshi is a Professor of Computer Science at the Georgia Institute of Technology. He is a member of the Hall of Fame of ISCA, Hall of Fame of MICRO, and Hall of Fame of HPCA. His research has been recognized with the best paper awards at MICRO 2018, CF 2019, and two selections (and three honorable mentions) at IEEE MICRO Top Picks. His ISCA-2009 paper on “Phase Change Memory” was awarded the 2019 Persistent Impact Prize and his MICRO-2009 paper on “Start-Gap Wear Leveling” was awarded the 2021 Persistent Impact Prize, both in recognition of “exceptional impact on the fields of study related to non-volatile memories”. He was the Program Chair of MICRO 2015 and Selection Committee Co-Chair of Top Picks 2017. He received the 2020 “Outstanding Researcher Award” from Intel and an “Outstanding Technical Achievement” award from IBM Research. He received his PhD (2007) and MS (2003) from the University of Texas at Austin.
Interests: multiprocessor architectures, thread-level speculation, energy-efficiency, hardware security, parallel computing
Bio: Josep Torrellas is the Saburo Muroga Professor of Computer Science at the University of Illinois. He is the Director of the Center for Programmable Extreme-Scale Computing, a Co-Leader of the Intel Strategic Research Alliance (ISRA) on Computer Security, and past Director of the Illinois-Intel Parallelism Center (I2PC). He serves as the Chair of IEEE TCCA, in the International Roadmap for Devices and Systems (IRDS), and is a Member of the U.S. National Academies Board on Army Research and Development. In the past, he has served in the Board of Directors of CRA and as a Council Member of CRA’s Computing Community Consortium (CCC). He is a Fellow of IEEE, ACM, and AAAS. He received the IEEE CS Harry H. Goode Memorial Award.
Interests: programming languages, compilers, accelerator design tools, approximate computing
Bio: Adrian Sampson is an assistant professor in the computer science department at Cornell. He works on programming languages, computer architecture, and the abstractions that separate them. He previously worked on approximate computing, the idea that we should allow machines to expose errors to some kinds of applications as a trade-off for computational efficiency. He sees approximate computing as an instance of a broader breakdown of airtight distinctions between hardware and software concerns.
The central theme of this workshop is to serve as a welcoming venue for junior graduate students and research-active undergraduate students to present their ongoing work and receive feedback from experts within the community. In addition, this workshop also aims to help early-stage graduate students in building connections both with their peers and established architects in the community. To this end, YArch will include:
– Route to Top-tier: Each submitted work will receive two or more expert reviews. The aim of these reviews will be to give early guidance on important boxes to check for the submitted work to be a future successful top tier conference paper.
– Meet an Architect: As part of the workshop, attendees will be paired with experts in their chosen research area to get feedback on their ongoing work and future research directions.
– Becoming an Architect: The workshop will include keynote talks from academic and industry leaders specifically geared towards early stage graduate students.
– Ask an Architect: The workshop will include a panel of established architects in industry and academia from whom students can seek career advice.
YArch strives to be an inclusive and diverse venue for Young Architects and below are some statistics to show how we performed along this dimension at YArch’20.
– Seven out of sixteen accepted student submissions were from female students.
– Of the sixteen accepted submissions, two were from Europe, three from Asia, and eleven from North America.
– One of the two keynote speakers was female.
– Of the five panelists, two were from industry and three from academia, including two female panelists.
– Of the three workshop organizers, one was from industry and two from academia, including one female organizer.
– Of the 33 PC members, ten were from industry and 23 from academia, including eight female members.
Eligibility: Applicants must be either
(a) research-active undergraduate students aiming for graduate school, or
(b) graduate students (Ph.D or Masters) in computer architecture and related fields who have completed less than 3 years of graduate school (Masters and/or PhD) at the time of the workshop.
A note from the student’s research advisor attesting this is required as part of the submission.
Call for Submissions: Eligible students are invited to submit their early stage or on-going work to this workshop. Submitted work should not have been presented as part of a prior ACM/IEEE conference.
The workshop invites papers from all areas of computer architecture, broadly defined. Topics of interest include, but not limited to:
– Datacenter systems
– Hardware acceleration
– Memory hierarchy
– Parallel architectures
– Emerging technologies
Note: This workshop is not a venue for publication and there will be no formal proceedings.
Submission guidelines: The goal of this workshop is to help students think about a problem/idea in an holistic manner and communicate your ideas to the wider community, so that we can provide some valuable early-stage feedback. To this end, we encourage you to cover the following aspects in your submission:
– Scope of problem/idea: Provide clear context for and scope of the problem(s) or idea(s) you intend to work on. This will likely form the basis of the introduction/background sections of your future work(s).
– Solution: Provide an overview of the design and implementation aspects of your solution(s) to the problem(s) described above. Given this is on-going work, focus more on providing breadth than depth. For example, beside describing the design of your idea, enlist the various system aspects which your proposed solutions will affect (e.g. does your proposed solution affect coherence protocols?) and that if you plan to discuss these effects in your future submission(s).
– Evaluation methodology: Discuss the evaluation methodology you plan to adopt to test the efficacy of your ideas. For example, the workloads that you plan to use, the tools you’ll employ (e.g., architectural simulator, real world experiments, FPGA prototypes), etc.
– Related work: This can be the traditional related work section. Please specify if you plan to quantitatively compare against some prior work.
– Submissions must be PDF files, in 2-column, single-spaced, 10pt format.
– Submissions must be at most 2 pages long, not including references.
– Submissions are double-blind. Please do not have any author identifying information in the paper submitted.
– Please have your research advisor send the workshop organizers an email with the following subject line “<Your name> meets YArch’21 eligibility requirements” to “email@example.com”.
– Submission site: https://yarch2021.hotcrp.com
– Submission deadline: February 17, 2021, 11:59pm EST
John Alsop, AMD Research
Alex Daglis, Georgia Tech
Mengjia Yan, MIT
Aasheesh Kolli, Google / Penn State University
Adrian Sampson, Cornell
Akanksha Jain, UT Austin
Akshitha Sriraman, University of Michigan
Andrew Lukefahr, University of Indiana
Arkaprava Basu, IISc Bangalore
Boris Grot, University of Edinburgh
Brandon Reagen, NYU
Caroline Trippel, Stanford
Christopher Fletcher, University of Illinois at Urbana–Champaign
Daniel Lustig, NVIDIA
Daniel Wong, UC Riverside
Dimitrios Skarlatos, CMU
Divya Mahajan, Microsoft
Elvira Teran, Texas A&M International University
Fangfei Liu, Intel
Gokul Ravi, University of Chicago
Jason Clemons, NVidia
Jayneel Gandhi, VMWare
Jishen Zhao, UCSD
Joseph Devietti, University of Pennsylvania
Joshua San Miguel, Wisconsin
Nuwan Jayasena, AMD Research
Onur Kayiran, AMD Research
Radha Venkatagiri, AMD Research / Oregon State University
Rangeen Chowdary, Intel
Rujia Wang, Illinois Tech
Saugata Ghose, University of Illinois at Urbana–Champaign
Shaizeen Aga, AMD Research
Swamit Tannu, University of Wisconsin-Madison
Tamara Silbergleit Lehman, University of Colorado Boulder
Tony Nowatzki, UCLA
Vincent Lee, Facebook Reality Labs Research
Vivek Menon, University of Southern California-ISI
Yatin Manerkar, University of Michigan
Yuhao Zhu, University of Rochester