Relevant Experience

Research Internships

  • Amazon Braket Science (Quantum Research), Seattle, Washington May 2022- July 2022
    Advisor: Yunong Shi, Eric Kessler
    Project Summary: Shaped the vision of AWS Braket’s quantum software stack for near-term quantum computers by establishing a systematic view of noise-aware compilation workflow and software error-mitigation. I also implemented a software framework for efficient native gate selection for quantum circuits to improve the fidelity of quantum programs.
    Publication: P. Das, E. Kessler, Y. Shi, “The Imitation Game: Leveraging CopyCats for Robust Native Gate Selection in NISQ Programs,” To Appear at HPCA, 2023
  • Google Quantum AI Research, Remote, California May 2021- July 2021
    Advisor: Cody Jones
    Project Summary: Designed a reconfigurable, lightweight, low latency, accurate lookup table decoder for studying quantum error correction in the near-term.
    Publication: P. Das, A. Locharla, C. Jones, “LILLIPUT: A Lightweight Low-Latency Lookup-Table Based Decoder for Near-term Quantum Error Correction,” ASPLOS, 2022
  • Microsoft Research, Redmond, Washington May 2019- July 2019
    Advisor: Nicolas Delfosse, Srilatha Manne, Doug Carmean
    Project Summary: Designed the micro-architecture of a fully pipelined Union-Find decoder to enable quantum error correction. This decoder is orders of magnitudes faster than existing designs (usually software). Also, proposed an optimized hardware-efficient system architecture to scale the design for large fault-tolerant quantum computers.
    Publication: P. Das, C. Pattison, S. Manne, D. Carmean, K. Svore, M. Qureshi, N. Delfosse, “AFS: Accurate, Fast, and Scalable Error-Decoding for Fault-Tolerant Quantum Computers,” HPCA, 2022
  • Microsoft Research, Redmond, Washington May 2018- July 2018
    Advisor: Doug Carmean
    Project Summary: Designed an accelerator for bitcoin mining and analyzed the trade-offs involved in system level logic design using superconducting technology. Also developed a methodology to analyze performance and resource estimates of superconducting designs using standard CMOS tools.
    Publication: S. Tannu, P. Das, M. Lewis, R. Krick, D. Carmean, M. Qureshi, “A Case for Superconducting Accelerators,” Computing Frontiers ( Best Paper Award), 2019

Full-Time Work Experience

  • NXP Semiconductors, Austin, Texas May 2016- August 2017
    Worked as a Digital Design Engineer in the Digital Networking Group where I designed PCIe controller and energy-efficient Ethernet modules for networking SOCs. I also defined the architecture and designed the control and reset block to support integration of various IPs in different SOCs.
  • LSI Corporation (now Broadcomm), Bangalore, India August 2012- August 2014
    Worked as an IC Design Engineer in the Custom Solutions Engineering Group where I worked on the design and verification of Ethernet and PCIe subsystems.

Teaching Experience

Graduate Course Co-Instructor

  • Introduction to Quantum Computing [CS 4803/ CS 8803 at Georgia Tech] Spring 2022

Graduate Teaching Assistantship

  • Advanced Computer Architecture [ECE 6100/ CS 6290 at Georgia Tech] Fall 2017, Spring 2018, Fall 2018
  • Digital Logic Design [ECE 316 at UT Austin] Spring 2015, Fall 2015, Spring 2016