Greetings! Welcome to the quarterly newsletter from the 3D Systems Packaging Research Center (PRC).
With advanced packaging taking center stage to continue Moore’s law, we at Georgia Tech are continuing to expand our activities in this important area through the PRC. We are an academic center with over 43 industry and 14 university collaborators spread across the globe. Our students in the center have grown significantly to nearly 60, with several undergraduate students now involved in research.
Recently I had an opportunity to share my thoughts on the microchip shortage facing the United States that might be of interest to many of you. https://research.gatech.edu/addressing-microchip-shortage.
MATERIALS FOR HETEROGENEOUS INTEGRATION
Emerging artificial intelligence (AI) applications require dense connectivity between integrated circuit (IC) chips to enable high-speed computations. Heterogeneous integration (HI) using advanced packaging is being viewed as a critical enabling technology for supporting AI applications. Such highly integrated systems require a multitude of materials to support electrical, mechanical, thermal, and chemical properties. In addition, the materials selected need to be compatible with panel level packaging processes including for example, Semi-Additive Processing (SAP) to ensure compatibility with low-cost manufacturing solutions. The inter-play between the various engineering domains makes the selection of materials, their processability, and compatibility extremely complex and very critical based on the applications.In this article from the PRC team led by Swaminathan, we review not only the future materials for HI but also survey the past and present work in this area. Read here.
State of the Art in Advanced Packaging (Left) and Thermal Interface Materials (TIM) used for Thermal Management (Right)
CHIP-TO-PACKAGE INTERCONNECTS FOR SUB-THZ WIRELESS APPLICATIONS
This work presents characterization of microvia interconnects in D-band frequencies for use as chip-to-package interconnects in Glass Panel Embedded (GPE) packages. Though, Antenna-in-Package (AiP) based on wafer-level fan out technology has demonstrated superior performance along with small form factor; embedding chips in glass panels in addition to AiP leverages the benefits of glass substrates and low-loss polymer buildup dielectrics while also mitigating the effects of wire-bond and microbumps for chip-to-package interconnects. This paper by Erdogan et al. at ECTC 2021demonstrates the fabrication and characterization of microvia transitions through polymer build-up film in D-band. Microvia transitions show an average loss of 0.146 dB in D-band with 0.177 dB maximum loss at 170 GHz. The < 0.2 dB loss in D-band reported here makes microvia transitions a promising alternative to either flip-chip or wire bond technologies. Read here.
Antenna-in-Package options using GPE (Left); Via transition and Conductor Backed Coplanar Waveguide (CBCPW) with 4 via transitions (Middle); Measured vs simulated via loss (Right)
IVRs FOR POWER DELIVERY ARCHITECTURES
Advances in High performance computing and AI related applications requires heterogeneous integration-based solutions where multiple chips with different functions are integrated in a package. Highly integrated package architectures require integrated voltage regulators (IVR) for achieving efficient power delivery solutions. This paper evaluates the design complexities resulting from integrating the voltage regulator with focus on three areas namely, electrical, thermal, and electromagnetics. Examples show that IVR benefits electrical power delivery performance while deteriorating noise coupling, thermal, and electromagnetic interference (EMI). A key finding from the paper based on multi-physics analysis illustrates that a micro-cooler based solution can be used to remove heat from embedded inductors. This work was published by graduate student Avula et al. in the IEEE Transactions on Components Packaging and Manufacturing Technology. Read here.
Heterogeneous Integration of power delivery architecture (Left) and Thermal solutions for IVR architecture (Right)
Dr. Suresh K. Sitaraman is a Regents’ Professor and a Morris M. Bryan, Jr Professor in the George W. Woodruff School of Mechanical Engineering at the Georgia Institute of Technology (Georgia Tech). Dr. Sitaraman is the Lead Faculty for NextFlex at Georgia Tech and directs the Flexible Wearable Electronics Advanced Research (www.flex.gatech.edu)Program. He also directs the Computer-Aided Simulation of Packaging Reliability Lab (www.caspar.gatech.edu). His expertise is in the areas of micro- and nano-scale structure fabrication, testing and characterization, and physics-based modeling and reliable design, as applied to flexible and rigid microsystems. Prior to joining Georgia Tech in 1995, Dr. Sitaraman was with IBM Corp. Dr. Sitaraman has co-authored more than 320 journal and conference publications. He has managed several research and development projects funded by US federal agencies, industry, and other sources totaling millions of dollars, and has mentored a vast array of post-doctoral fellows as well as doctoral, master’s, bachelor’s, and high-school students. Dr. Sitaraman is an ASME Fellow.
Pragna Bhaskar is pursuing Ph.D. in Material Science and Engineering at 3D Systems Packaging Research Center. She is advised by Prof. Madhavan Swaminathan and Prof. Mark Losego. Her research interests include ultra-low-k dielectric materials, reliability, and fabrication. Prior to starting her Ph.D. at Georgia Tech, she was a scientific officer at Indira Gandhi Center for Atomic Research, Kalpakkam, India. She completed her bachelor’s degree from National Institute of Technology, Tiruchirappalli in 2008 and master’s degree from Indian Institute of Technology Madras in 2010. She was awarded the DAE graduate fellowship for the years 2008-10 and Sudarshan Bhat memorial prize in 2010.
Congratulations to our Recent grad!
Sridhar Sivapurapu, Ph.D.
Employer: Qualcomm, USA
Upcoming & RECENT Events
- Distinguished Lecture (Virtual): Reliability Assessment for Heterogeneously Integrated Package by Professor Ganesh Subbarayan. April 7, 2022 at 11:00 AM EST. Registration is required and can be done at https://tinyurl.com/GTPRCSubbarayan22
- PRC Industry Advisory Board meeting May 26 and 27, 2022 (by invitation only).
- PRC Summer Youth Program for high school students 16 and 17 years old. June 13 – July 22, 2022. See FLYER for additional information.
- SAVE THE DATE for Workshop – Electric Drives for E-Aviation: System Topology, Packaging & Thermal Technologies. August 8 – 9, 2022 from 11:00 AM – 3:00 PM. Registration required. Additional information is forthcoming.
- Distinguished Lecture (Virtual): Semiconductor Packaging: The Future Is Now by Professor Madhavan Swaminathan, Silicon Valley Area Chapter, Apr. 14, 2022. Registration at https://r6.ieee.org/scv-eps/?p=2902