For artificial intelligence (AI) applications there is a trend towards non-Von Neumann machines. Von Neumann machines are built around an architecture that requires CPU, fast access RAM and slow to access Hard Drive. Such an architecture is limited by latency and often consumes large amounts of power. In contrast, non-Von Neumann machines are built on the premise that logic resides in memory leading to low latency. Such co-location of logic and memory is leading to in-memory and near-memory computing paradigms requiring massively parallel architectures with dense connectivity using vertical CMOS and beyond CMOS device technologies, with access to large amounts of memory in close proximity. The resulting neural network, as shown in Figure 1 should be suitable for life-long learning and decision making in a changing environment.
Figure 1: Neural Network with advanced devices
Three important metrics drive computing for AI namely, data rate, energy/bit (EPB) and throughput. The focus here is on short distance (1-2mm) communication between adjacent chips, where multiple interconnects (1000+) constitute a lane, and multiple lanes are used to meet the bandwidth requirements within the module. The fourth and fifth important metrics are power delivery and SerDes, covered under power and emerging technologies. The PRC focus is shown in Table 1 and compared to state of the art.
Table 1: Metrics for Computing
The PRC technology focus is shown in Figure 2 which consists of a glass core with 100-300mm thickness, with patterned polymer and metal layers on either side. The module supports fine lines and spaces with fine pitch die assembly. Due to the tailored coefficient of thermal expansion (CTE) of glass, the module can be directly assembled onto a printed circuit board (PCB), as shown in the figure. The research focus areas are: a) Machine Learning based design and optimization of the glass module, b) glass panel embedded (GPE) packaging, c) development of panel scale RDL processes that support 1um lines and spaces with 4:1 aspect ratio, d) fine pitch (<20um) copper-copper bonding between chip-substrate and e) module reliability for large body sizes.