Common Heterogeneous Integration and IP Reuse Strategies (CHIPS)


The goal of the DARPA CHIPS program is to establish and demonstrate a modular design and fabrication flow for electronic systems while addressing the rising cost, lead-time, and complexity of IC design. The central idea is that a system can be subdivided into functional circuit blocks or chiplets that are reusable IP blocks. Complete electronic systems can then be created through integration of chiplets on an interposer, rather than through the design and fabrication of circuits in a monolithic flow. This approach is expected to expand access to a large catalog of off-the-shelf IP blocks, allow reuse of existing IP blocks, and speed heterogeneous integration of blocks in other technologies and nodes.


Our team at Georgia Tech, partnering with Cadence, offers EDA solutions to assist other teams working on CHIPS demonstrations. Our goal is to help CHIPS designers develop commercial-grade solutions that meet the given power, performance, and area (PPA) and cost saving goals while minimizing human intervention. During phase 1, our tool will help in converting individual IP blocks into chiplets based on the agreed interface standards. In phase 2, our tool will help integrate and optimize chiplets onto an interposer to form a complete 2.5D system. Our tool in phase 3 will support upgrades and swaps of the chiplets. Acknowledging the availability of commercial EDA tools that handle IP design and verification, our focus will be threefold: (1) creating new methodologies to seamlessly integrate existing commercial engines, (2) enhancing the capability of existing commercial engines and algorithms, (3) developing new engines that are missing to handle 2.5D chiplet integration and upgrades. We will utilize Cadence Stratus high-level synthesis tool, Cadence Innovus physical design tool, and Cadence Allegro package design tool as our main baseline engines.

Our automated flow encompasses architecture, circuit, and package design phases to automate chiplet creation and integration. Our flow accepts soft and hard IPs, where soft IPs are represented in RTL or GDS layouts, and hard IPs in fabricated chips. In our flow, soft IPs are converted into chiplets, where automatically generated wrapper codes are added in each RTL to cope with standard and protocol mismatches among chiplets. These RTLs are synthesized and laid out using a commercial place/route tool. Lastly, we add level converter and interface circuitries to handle signaling with other chiplets that run at different speed, supply voltage, and node. On the other hand, the wrapper for a hard IP is integrated into our new concept named switch chiplet. Additionally, switch chiplet offers physical connections among chiplets so that all traffic among chiplets are handled by the switch chiplet except for those that we decide to bypass it.

Once the physical layouts of all chiplets are created, they are mounted and connected onto a target interposer platform using our interposer tool. Clock and power delivery from I/O bumps is made using interposer interconnects including TSVs. Our additional goal in interposer design is to ensure thermo-electro-mechanical reliability. Our chiplet-based system operates under globally asynchronous locally synchronous (GALS) approach, where computing and communication within the boundary of chiplets are done using a global clock. However, the communication among chiplets is done asynchronously, where the messages are produced, delivered, and consumed on a need basis utilizing FIFO buffers. Our innovations include interface synthesis, switch chiplet concept, and chiplet-oriented chip/package co-design tools.​



Published Papers


•Tushar Krishna •Sungkyu Lim(PI)  •Saibal Mukhopadhyay  •Madhavan Swaminathan