Director’s Corner
Greetings! Merry Christmas and Happy Holidays!
Welcome to the PRC Quarterly Newsletter. We are an academic
center based at Georgia Tech (GT) focusing on next generation advanced packaging and system integration. Our team consists of 29 faculty from five schools, 11 research/administrative staff, 50+ graduate/undergraduate students, and several visiting engineers. As a team we work with 41 industry/government organizations and 14 universities on collaborative research and education projects. Our research focus is in heterogeneous integration and advanced packaging related to emerging applications in artificial intelligence, high performance computing, automotive electronics, wireless, space, and many more.
To learn more about the PRC please view our short video: https://www.youtube.com/watch?v=lqPW8h2EjyA.
Our second virtual Industrial Advisory Board (IAB) meeting was held Nov. 10-12, 2020 and repeated twice to cover our members and collaborators in North America, Europe and Asia. This meeting was spread over six sessions, attended by 157 people and very lively through the many discussions and feedback from industry. We provide below some recent research highlights.
Sincerely,
– Madhavan Swaminathan, PRC Director
Research Highlights
Demystifying Machine Learning for Package Design
Semiconductor packages are becoming increasingly complex to design which has led to the development of machine learning (ML) based techniques to ease and simplify the design process. In a recent invited paper titled “Demystifying Machine Learning for Signal and Power Integrity Problems in Packaging”, published in IEEE Transactions of Components, Packaging, and Manufacturing Technology, 2020, the fundamentals of ML are explained and explored as they relate to fast model development, protecting intellectual property and design optimization Read here. A tutorial based on this paper is available at https://www.youtube.com/watch?v=qrjU6Hj6ruY&feature=youtu.be.
Basics of Machine Learning (left) and Machine Learning Procedure (right)
Silicon or Organic Interposer – Which is better?
Heterogeneous chiplet integration is becoming a critical area for the semiconductor industry. Identifying the optimal interposer substrate is key to designing a high performance, reliable and cost-effective system. In a recent paper titled “Silicon vs. Organic Interposer: PPA and Reliability Tradeoffs in Heterogeneous 2.5D Chiplet Integration”, presented at the IEEE International Conference on Computer Design (ICCD), a quantitative comparison between two 2.5D IC designs based on silicon and liquid crystal polymer (LCP) interposer technologies was conducted at the system level for the first time. The two designs were gauged for several metrics such as Power Performance and Area (PPA), Signal/Power integrity and Cost. The paper authored by graduate student J. Kim, his advisor Prof. S. Kim and others was recognized with the Best Paper Award at ICCD 2020. Read here
Physical layout and IR drop map of RocketCore Chiplet (28nm) in Silicon (left) and Organic (right) interposer
Socketable BGAs by surface modification of solder spheres with multi-layered metallic coatings
Land Grid Arrays (LGAs) and Ball Grid Arrays (BGAs) are the board-level interconnection technologies of choice for a large number of packaged ICs. These technologies are currently used in socketing and surface mount (SMT) applications, respectively, but there is a growing need to converge to a single package design to reduce the cost and processing times of manufacturing packages with two separate interconnection technologies. Moreover, solder BGAs, when used directly in sockets, face multiple challenges such as damage to the solder surface and increase in contact resistance over time due to the formation of surface oxides and intermetallics at the socket-solder interface. To enable socketable BGA packages, PRC researchers have pioneered a new class of solder spheres with custom-designed thin-film metallic coatings, resulting in universal BGA packages that can be used alternatively in socketing and SMT applications. These multi-layered metallic coatings of Ni-Au and Bi-Au were precisely designed to control the interfacial reactions in the interconnection system throughout the component lifetime. The coating deposition and ball-attach processes were developed, characterized and optimized by the PRC-team, and this technology is now ready for qualification in application test vehicles. In a recent paper published by graduate student O. Gupte, details of the thermal aging reliability of BGA packages fabricated using this new interconnection technology is described, for assessing the applicability of such packages in socketing applications. His co-authors are G. Murtagian, R. Tummala and V. Smet, and the paper was published in the IEEE Transactions of Components, Packaging, and Manufacturing Technology, 2020. Read here
Package fabricated with Ni-Au coated solder spheres (left), Top view of uncoated solder sphere and Ni-Au coated solder sphere (center) and, Cross-section view of Ni-Au coated solder sphere attached to the package with Sn57.6Bi0.4Ag (SBA) solder (right)
Breakthrough in Microvia Technology – 20 μm to 3 μm Via Diameters and 50 μm to 8 μm in via pitches
Microvia is a key element in redistribution layer (RDL) for advanced packaging substrates, interposers and Fan-Out packages. Currently, the IC industry has been steadily advancing towards 5nm node with further reductions projected in the near future to progressively create large numbers of input/output (IO) at fine pitch. Today the organic interposer redistribution layer can only achieve an IO density of ~40 IOs/mm/layer with line/space of 6μm and microvia diameter of 20μm at 50μm pitch. However, to further increase IO density, RDL with 1μm line/space together with 1-2μm diameter microvias are required. To break this boundary, studies of microvia ablation using a picosecond UV laser were performed. Picosecond laser pulses with the higher peak power and shorter pulse durations can be used to ablate dielectric materials with less heat produced which ensures smaller heat affected zones compared to other pulsed laser sources. By employing ultrashort laser pulses with Gaussian beam profiles, experiments performed at PRC showed that the typical 5μm via diameter in ABF GX-92P films can be scaled down to 2μm using 80nm thick copper. This thin copper (referred to as a barrier layer) acts as a hard mask for producing smaller microvias in the underlying dielectric layer. Microvias with 3μm diameter was demonstrated using the nanometer copper barrier layer. This work was published by F. Liu with co-authors R. Zhang, G. Khurana, B.H. Deprospo, R. R. Tummala, and M. Swaminathan in the paper titled “Smaller Microvias for Packaging Interconnects by Picosecond UV Laser with a Nanometer Metal Barrier” in IEEE Transactions of Components, Packaging, and Manufacturing Technology, vol 10, No. 8, August 2020. Read More
Comparison of laser microvia ablation on bare Dielectric with barrier copper layer (left); SEM Image of a microvia with 3 µm diameter in ABF GX-92P (center) and FIB/SEM Image of microvia cross section with via pitch 8µm in ABF GX-92P (right)
Faculty Highlight
For a second year in a row, Prof. C. P. Wong was one of 12 faculty members at Georgia Tech who was identified among highly cited researchers by the Web of Science. Prof. C. P. Wong is the Charles Smithgall Institute Endowed Chair and Regents’ Professor in the School of Materials Science and Engineering. Prior to joining Georgia Tech, he was with AT&T Bell Laboratories for many years and became an AT&T Bell Laboratories Fellow in 1992. He holds over 65 U.S. patents, numerous international patents, has published over 1000 technical papers, 12 books and is a member of the National Academy of Engineering of the USA since 2000, and a foreign academician of the Chinese Academy of Engineering since 2013.
His research interests lie in the fields of polymeric materials, electronic packaging and interconnect, interfacial adhesions, nano-functional material syntheses and characterizations, nano-composites such as well-aligned carbon nanotubes, graphenes, lead-free alloys, flip chip underfill, ultra-high k capacitor composites and novel lotus effect coating materials.
Student Spotlight
Claudio Alvarez Barros received the B.S. degree in electrical engineering from the Universidad de Santiago de Chile in 2009. From 2010 to 2012, he worked in the international ALMA Radio Observatory and subsequently worked in other companies as an electronic and robotic engineer. In 2016, he was granted a Fulbright fellowship from the US government and a CONICYT scholarship from the government of Chile to pursue a Ph.D. degree in the United States and in 2017, he started the Electrical and Computer Engineering Ph.D. program at the Georgia Institute of Technology. Claudio received his M.S. degree from Georgia Tech in 2019 and is currently a Ph.D. student. His research interests include signal and power integrity and power electronics. In Summer 2020, he completed an internship at Intel Corporation.
Congratulations to our 2020 Graduates!
Tong-Hong Lin, Ph.D.
Thesis: Applications of Additive Manufacturing Technologies to Ambient Energy Harvesters for Microwave and Millimeter-Wave Autonomous Wireless Sensing Networks and 3D Packaging Integration
Employer: Apple (CA)
Atom Watanabe, Ph.D.
Thesis: Design and Demonstration of High-Performance Ultra-thin Antenna-Integrated 3D Glass-based mm-wave Packages
Employer: Qualcomm (San Diego, CA)
Hakki M. Torun, Ph.D.
Thesis: Machine Learning based Design and Optimization for High-performance Semiconductor Packaging and Systems
Employer: Apple (San Diego, CA)
Muhammad Ali, Ph.D.
Thesis: Modeling, Design and Fabrication of Miniaturized, High Performance and Integrated Passive Components for 5G and mm-Wave Applications
Employer: Apple (CA)
Bart Deprospo, Ph.D.
Thesis: Modeling, Design and Demonstration of 1μm Wide Low Resistance Panel Redistribution Layer
Technology for High Performance Computing Applications
Employer: Novellus (Kennesaw, GA)
Tailong Shi, Ph.D.
Thesis: Modeling, Design, Fabrication And Demonstration of Ultra-Thin, High-performance Glass Panel Embedded (GPE) Packages For mm-Wave Applications
Haksun Lee, Ph.D.
Thesis: Design and Demonstration of 3D Stacked SiC Power Module with Superior Electrical Parasitics, and Thermal Performance
Employer: TI (Dallas, TX)
Rui Zhang, Ph.D.
Thesis: Integration of optoelectronics interconnects on glass interposers for high speed communications.
Employer: Alpha and Omega Semiconductor (CA)
Upcoming Events
Distinguished Lecture (Virtual) – Dr. Ivan Ndip, Head of Fraunhofer IZM Branch Lab for High-Frequency Sensor Systems Cottbus; Date: January 2021, exact date TBD (Open to all attendees; Registration required).